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PS-702
SAW Based Clock Oscillator Former Part Number SO-720
PS-702
Description
The PS-702 is a SAW Based Clock Oscillator that achieves low phase noise and very low jitter performance. The PS-702 is housed in an industry standard 6-Pad leadless ceramic package that is hermetically sealed. Packaging options include bulk or tape and reel.
Features
* * Industry Standard Package, 5.0 x 7.5 x 2.0 mm ASIC Technology For Ultra Low Jitter 0.100 ps-rms typical across 12 kHz to 20 MHz BW 0.120 ps-rms typical across 50 kHz to 80 MHz BW * * * * * * * Output Frequencies from 150 MHz to 1 GHz 3.3 V Operation LV-PECL or LVDS Configuration with Fast Transition Times Complementary Outputs Output Disable Feature Improved Temperature Stability over Standard SAW XO Product is free of lead and compliant to EC RoHS Directive * * * * *
Applications
Reference Clock for Wired and Wireless Products Description Standard
1-2-4 Gigabit Fibre Channel 10 Gigabit Fibre Channel 10GbE LAN / WAN OC-192 SONET / SDH INCITS 352-2002 INCITS 364-2003 IEEE 802.3ae ITU-T G.709 GR-253-CORE Issue4
Block Diagram
Vcc COutput Output
BAW
SAW
Vc
OD
Gnd
Page1 of 7 Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
Rev: 08May2009
Performance Specifications
Table 1: Electrical Performance Parameter
Voltage 2, 3 Current (No Load)
3
Symbol
VCC ICC
Min
Supply 2.97 Frequency
Typical
3.3 55
Maximum
3.63 70 1000
Units
V mA MHz ppm
Nominal Frequency
1, 2
fN fSTAB
150 50, 100
Frequency Stability 1, 2 (Ordering Option) Aging 6, 8
10 Outputs VCC-1.4 450 250 IOUT
5, 6
ppm V mV-pp V mV-pp
Mid Level - LVPECL 2, 3 Swing - LVPECL Swing - LVDS 2, 3 Current 6 Rise Time Fall Time 5, 6 Symmetry
6, 7 2, 3 2, 3 2, 3
VCC-1.25 600 VCC-1.2 450
VCC-1.0 750
Mid Level - LVDS
20 500 500 45 50 0.100 0.120 2.5 16 0/70, -20/70 or -40/85 5.0 x 7.5 x 2.0 55 0.250 0.300 3.0 24
mA ps ps % ps-rms ps-rms ps-rms ps pk-pk C mm
tR tF SYM J J J J TOP
Jitter (12 kHz - 20 MHz BW) 622.08 MHz Jitter 6, 7 (50 kHz - 80 MHz BW) 622.08 MHz Period Jitter 9, RMS (622.08 MHz) Period Jitter , Peak - Peak (622.08 MHz) Operating Temperature Package Size
1] 2] 3] 4] 5] 6] 7] 8] 9]
1 9
See Standard Frequencies and Ordering Information tables (Pg 7) for more specific information Parameters are tested with production test circuit below (Fig 1). Parameters are tested at ambient temperature with test limits guard-banded for specified operating temperature. Measured as the maximum deviation from the best straight-line fit, per MIL-0-55310. Measured from 20% to 80% of a full output swing (Fig 2). Not tested in production, guaranteed by design, verified at qualification. Integrated across stated bandwidth per GR-253-CORE Issue4. Tested with Vc = 0.3V to 3.0V unless otherwise stated in part description Broadband Period Jitter measured using Lecroy Wavemaster 8600A 6 GHz Oscilloscope, 250K samples taken
Enable, Disable (-1.3V, +2.0V)
1
6
(+2.0V)
tR
COutput
tF
No connect
2
5
VOH 50% VOL
(-1.3V)
3
4 50
Output
50
On Time
Test Circuit Notes: 1) To Permit 50 Measurement of Outputs, all DC Inputs are Biased Down 1.3V. 2) All Voltage Sources Contain Bypass Capacitors to Minimize Supply Noise. 3) 50 Terminations are Within Test Equipment.
Period
Fig 1: Test Circuit
Fig 2: LV-PECL Waveform
Page2 of 7 Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
Rev: 08May2009
Absolute Maximum Ratings Parameter
Power Supply Output Current Storage Temperature Soldering Temp/Time
Symbol
VCC IOUT TS TLS
Ratings
0 to 4 25 -55 to 125 260 / 40
Unit
V mA C C / sec
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied at these or any other conditions in excess of conditions represented in the operational sections of this datasheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Permanent damage is also possible if OD or Vc is applied before Vcc.
Suggested Output Load Configurations
+3.3V 0.10 F 0.01 F 0.10 F 0.01 F
+3.3V
+3.3V
150
150
OD N/C Gnd
1 2 3
6 5 4
Vcc COutput Output Z = 50 Z = 50 100
OD N/C Gnd
1 2 3
6 5 4
Vcc 40 COutput Output Z = 50 Z = 50 40
49
49
240
240
LV-PECL to LV-PECL: For short transmission lengths, the power consumption could be reduced by removing the 100 resistor and doubling the value of the pull down resistors.
LV-PECL to LVDS: Restricted for short transmission lengths. Configuration may require modification depending on LVDS receiver.
+3.3V 0.10 F 0.01 F 0.10 F 0.01 F
+2.0V
OD N/C Gnd
1 2 3
6 5 4
Vcc COutput Output 0.01 F 0.01 F
OD N/C -1.3V
1 2 3
6 5 4
Vcc COutput Output
240
240
Functional Test: Allows standard power supply configuration. Since AC coupled, the LV-PECL levels cannot be measured.
Production Test: Allows direct DC coupling into 50 measurement equipment. Must bias the power supplys as shown. Similar to Figure 1.
Page3 of 7 Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
Rev: 08May2009
Typical Characteristics - Phase Noise
PS-702-ECE-GAAN-622M080000
Page4 of 7 Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
Rev: 08May2009
Reliability
VI qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR reflow simulation. The PS-702 family is capable of meeting the following qualification tests: Environmental Compliance Parameter
Mechanical Shock Mechanical Vibration Solderability Gross and Fine Leak Resistance to Solvents
Conditions
MIL-STD-883, Method 2002 MIL-STD-883, Method 2007 MIL-STD-883, Method 2003 MIL-STD-883, Method 1014 MIL-STD-883, Method 2016
Handling Precautions
Although ESD protection circuitry has been designed into the PS-702 proper precautions should be taken when handling and mounting. VI employs a human body model (HBM) and a charged device model (CDM) for ESD susceptibility testing and design protection evaluation. ESD Ratings Model
Human Body Model Man Man Model
Minimum
1500V 200V
Conditions
MIL-STD-883, Method 3015 V/JESD22-A115-A
Reflow Profile (IPC/JEDEC J-STD-020C) Parameter
PreHeat Time Ramp Up Time Above 217 C Time To Peak Temperature Time at 260 C Ramp Down
Symbol
tS RUP tL TAMB-P tP RDN
Value
60 sec Min, 180 sec Max 3 C/sec Max 60 sec Min, 150 sec Max 480 sec Max 20 sec Min, 40 sec Max 6 C/sec Max
The device is qualified to meet the JEDEC standard for Pb-Free assembly. The temperatures and time intervals listed are based on the Pb-Free small body requirements. The PS-702 device is hermetically sealed so an aqueous wash is not an issue. Termination Plating: Electroless Gold Plate over Nickel Plate
Page5 of 7 Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
Rev: 08May2009
Outline Drawing & Pad Layout
Pin Out Pin
1
Symbol NC or OE
1
Function
NC or Enable = LV-CMOS logic 0 or Ground Disable = LV-CMOS logic 1 **see Note 1 below** NC or Enable = LV-CMOS logic 0 or Ground Disable = LV-CMOS logic 1 **see Note 1 below** Case and Electrical Ground Output Complementary Output Power Supply Voltage (3.3V 10%)
2
NC or OE1
3 4 5 6
GND Output COutput
VCC
Note 1: For proper operation disable pin can not be left floating and a pin1 or pin 2 enable option must be ordered. See page 7 for alternative input logic operation
Tape & Reel (EIA-481-2-A)
Tape Dimensions (mm) Dimension Tolerance
PS-702
Reel Dimensions (mm) Po Typ
4
W Typ
16
F Typ
7.5
Do Typ
1.5
P1 Typ
8
A Typ
178
B Min
1.5
C Typ
13
D Min
20.2
N Min
50
W1 Typ
16.4
W2 Max
22.4
# Per Reel
200
Page6 of 7 Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
Rev: 08May2009
Standard Output Frequencies (MHz)
155M520000 240M000000 320M000000 491M520000 635M040000 690M569200 800M000000 156M250000 245M760000 324M000000 500M000000 637M500000 693M483000 901M120000 160M000000 250M000000 350M000000 531M250000 640M000000 704M380600 1000M00000 162M000000 260M000000 375M000000 532M000000 644M531300 707M352700 175M000000 268M800000 384M000000 533M000000 657M421900 720M000000 187M500000 300M000000 389M600000 537M600000 666M514300 742M434700 200M000000 311M040000 400M000000 622M080000 669M326600 768M000000 212M500000 312M500000 480M000000 625M000000 672M162700 796M875000
Frequencies not shown are available upon request.
Ordering Information
PS - 702 - E C E - K A A N - xxxMxxxxxx
Product Family PS: SO - SAW Oscillator Package 702: 5 x 7.5 x 2.0 mm 6 Pad Ceramic SMD Input E: 3.3 Vdc 10% Output C: LV-PECL (45/55% Symmetry) D: LVDS (45/55% Symmetry) Operating Temperature T: 0C to 70C J: -20C to 70C E: -40 to 85 C Frequency (See Above) 150 - 1000 MHz Future Use Enable/Disbale Pin A: Pin 1 B: Pin 2
Enable/Disable A: Enable High, Tristate B: Enable High, Fixed Logic Level C: Enable Low, Tristate D: Enable Low, Fixed Logic Level Stability K: 50 ppm maximum S: 100 ppm maximum
*Not all combinations are possible
For Additional Information, Please Contact
USA:
Vectron International 267 Lowell Road Hudson, NH 03051 Tel: 1.888.328.7661 Fax: 1.888.329.8328
Europe:
Vectron International Landstrasse, D-74924 Neckarbischofsheim, Germany Tel: +49 (0) 3328.4784.17 Fax: +49 (0) 3328.4784.30
Asia:
Vectron International 1F-2F, No 8 Workshop, No 308 Fenju Road WaiGaoQiao Free Trade Zone Pudong, Shanghai, China 200131 Tel: 86.21.5048.0777 Fax: 86.21.5048.1881
Disclaimer
Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Page7 of 7 Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
Rev: 08May2009

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